Building a RISC-V CPU Core (LFD111x) - Ubbergo

Building a RISC-V CPU Core (LFD111x)

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Course type

Level

Beginner

Time/Effort

5-7 hours

Created by

The Linux Foundation

Provider

Session type

Self-paced

Pricing

Instalments

N/A

Certificate

Optional paid

Projects

Labs & Assignments

Tutor support

In course forum

Access

7 weeks

More features

Discussions forums, Graded Quizzes (for paid certificate only)

Language

English

Subtitles

N/A Subtitles

Skills Covered: RISC-V CPU, The Role of RISC-V, Digital Logic, RISC-V-Subset CPU, Completing RISC-V CPU, Basic CPU Microarchitecture, Transaction-Level Verilog, Makerchip online IDE

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ABOUT THIS COURSE


This course is dedicated for someone with a technical background who wants to learn more about hardware. If you are new to digital reasoning or a seasoned veteran, students will leave with new abilities that they can put to use right away. There is no prerequisite knowledge of digital logic architecture available.

This course provides students with hands-on experience with RISC-V and advanced circuit design software. You will leave with fundamental skills for a career in logic design, as well as the ability to use the emerging Transaction-Level Verilog language extension (even though you don’t already know Verilog).

 

WHAT YOU WILL LEARN


This is a crash course in basic CPU microarchitecture and digital logic design. You’ll incorporate everything from logic gates to a basic but full RISC-V CPU core using the Makerchip online integrated development environment (IDE).

What you can do with open source programming tools that are freely available online would amaze you. You’ll learn about RISC-V, Transaction-Level Verilog, and the online Makerchip IDE, as well as other new innovations that promote an open-source hardware ecosystem.

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Building a RISC-V CPU Core (LFD111x)
Building a RISC-V CPU Core (LFD111x)

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